Interrupts

Interrupts are a mechanism for allowing peripherals to signal to the computer’s CPU that they require attention. Dedicated wires are used to connect with all of the peripherals connected to the computer. When a peripheral requires attention it sends a unique signal to the CPU for it to stop what it is doing and service the peripheral. In other words the CPU has to interrupt the current operation to deal with the peripheral.

Once the CPU has identified the peripheral that requires attention, control of the processor is passed to a small program, called an interrupt handler or interrupt service routine (ISR), which deals with the peripheral. These interrupt handlers are programmed to be as small and as fast as possible so that the program that was originally running is interrupted for as short a time as possible. The sequence of events is therefore as follows:

1.    Interrupt is raised
2.    Current CPU instruction is completed
3.    Contents of internal registers are stored in (pushed onto) the  stack
4.    The memory address of the ISR is found and transfer controlled
5.    ISR is run
6.    Internal register contents are restored (popped) from the stack
7.    Original process continues from where it was stopped

As interrupts stop a currently running process, the state of which must be saved before the interrupt is handled, there is a lag between the interrupt being generated and the ISR being run. This lag is the interrupt latency and is a consequence of steps 2, 3 and 4 above.

Interrupts usually have a hierarchy, defined by the computer system designer, which decides which interrupts have the highest priority. If an interrupt service routine is itself interrupted then the priority of the interrupt is checked. If the new interrupt is of a higher priority then it is serviced, if not, it is ignored. This is a nested interrupt system.

There is a possibility that an interrupt with a low priority may be lost. While for some peripherals this may not matter too much, for others it may be disastrous. Peripherals that must be serviced within a specific time are assigned a non-maskable interrupt (NMI). These NMIs override all other interrupts.

Next: Interrupt Identification